Title:
SCANNING CONVERTING CIRCUIT
Document Type and Number:
Japanese Patent JPH08331517
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To facilitate an ASIC by forming a scan system conversion circuit which is an address generator for scan system conversion, only with a pure logic circuit. SOLUTION: An up/down counting circuit part 1 up counts values from one to N-1 and then down counts to one. A down-counting circuit part 2 counts down from an output value of the 1 to zero and generates a carry signal. A 1st selecting part 3 alternately selects values of the N-1 and -(N-1) and outputs them. A 2nd selecting part 4 alternately selects values one and N and outputs them. A 3rd selecting part 5 selects final output data with the outputs of the parts 3 and 4 as inputs. A phase-converting circuit part 7 changes an output phase of the part 4 at the point of time, when the N-1 or the -(N-1) has occurred at N-1 times. An accumulating part 8 generates a final address output signal by accumulating the outputs of the part 5.
Inventors:
BUN YOUSEKI
KIN SHICHIYUU
CHIYOU JIYUNKA
KIN SHICHIYUU
CHIYOU JIYUNKA
Application Number:
JP18698995A
Publication Date:
December 13, 1996
Filing Date:
July 24, 1995
Export Citation:
Assignee:
KOREA ELECTRONICS TELECOMM
International Classes:
H04N7/01; H04N1/41; H04N19/42; H04N19/423; H04N19/60; H04N19/625; (IPC1-7): H04N7/01
Attorney, Agent or Firm:
Minoru Yoshida (2 outside)