Title:
SELF-SYNCHRONIZING TYPE PIPE LINE DATA PATH CIRCUIT, AND NON-SYNCHRONIZING SIGNAL CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JP3856892
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To control finely for reducing the power consumption, by applying a MT-CMOS circuit to a self-synchronizing pipe line data bus circuit.
SOLUTION: Combination circuits 11A, 12A consisting of MT-CMOS circuits are connected between REG1-REG3, produce activation signals ST1, ST2 corresponding to a request signal REQi by a asynchronous signal control circuit 13A, and controls the activation of this combination circuits 11A, 12A. Especially, this transition from activation to sleep is performed based on request signals REQ2, REQ3 generated by monitor circuits 131, 132 considering a signal transmission delay time in the combination circuit.
Inventors:
Koji Fujii
Takakuni Doseki
Takakuni Doseki
Application Number:
JP6169697A
Publication Date:
December 13, 2006
Filing Date:
March 03, 1997
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
G06F7/00; G06F1/32; G11C19/28; G06F9/38; (IPC1-7): G11C19/28; G06F7/00
Domestic Patent References:
| JP6350435A | ||||
| JP3286224A | ||||
| JP7086916A |
Attorney, Agent or Firm:
Tsuneaki Nagao
Previous Patent: SURFACE REFORMING METHOD OF HARD MATERIAL AND CUTTING TOOL
Next Patent: PIPE LINE END MACHINING STRUCTURE AND MACHINING METHOD
Next Patent: PIPE LINE END MACHINING STRUCTURE AND MACHINING METHOD