Title:
SEMICONDUCTOR BOOSTING CIRCUIT
Document Type and Number:
Japanese Patent JP3489912
Kind Code:
B2
Abstract:
PURPOSE: To prevent the deterioration of the boosting ability of a boosting circuit using MOS transistors caused by substrate effects.
CONSTITUTION: Each boosting step of a semiconductor boosting circuit is constituted of each pair of MOS transistors Q1 and Q3, Q5 and Q7,... connected in parallel with each other and the rise of the threshold voltage of each MOS transistor caused by a substrate effect is suppressed by electrically separating the substrate sections of the transistors from each other in each step and, at the same time, respectively connecting the substrate sections in each step to the source terminals N3, N4,... of the transistors Q1 and Q3, Q5 and Q7,... and respectively fixing each substrate section to the source potential of the transistors Q1 and Q3, Q5 and Q7,... in each step. Therefore, the transistors Q3, Q7,... prevent the turning on of P-N junctions parasitically existing between the transistors Q1, Q5,... and substrate sections.
Inventors:
Kikuzo Sawada
Application Number:
JP15389895A
Publication Date:
January 26, 2004
Filing Date:
May 29, 1995
Export Citation:
Assignee:
Nippon Steel Corporation
International Classes:
G11C17/00; G11C16/06; H01L21/822; H01L27/04; H01L29/78; H02M3/07; (IPC1-7): H02M3/07; G11C17/00; H01L21/822; H01L27/04; H01L29/78
Domestic Patent References:
| JP6276729A | ||||
| JP63141359A | ||||
| JP6209238A |
Attorney, Agent or Firm:
Koetsu Kokubun