Title:
SEMICONDUCTOR CHIP
Document Type and Number:
Japanese Patent JP2001094043
Kind Code:
A
Abstract:
To prevent corrosion of a pad and an internal wiring in an analysis test, which is performed by taking out a semiconductor chip from a package.
A first barrier metal film 17, a test wire connection film 18 and a second barrier metal film 19 are laminated on an aluminum pad 14, in the order from the bottom. A bump BM is protruded and formed on the second barrier metal 19. In an analysis test of a semiconductor device, the second barrier metal 19 exposed by removing the bump BM is removed with an etchant. A test wire W is connected with the exposed test wire connection film 18, and an operation confirming test of a master chip 1 is conducted.
Inventors:
UEDA SHIGEYUKI
Application Number:
JP26574299A
Publication Date:
April 06, 2001
Filing Date:
September 20, 1999
Export Citation:
Assignee:
ROHM CO LTD
International Classes:
H01L23/52; H01L21/3205; H01L21/66; H01L23/50; H01L25/065; H01L25/07; H01L25/18; (IPC1-7): H01L25/065; H01L21/66; H01L23/50
Attorney, Agent or Firm:
Kousaku Inaoka (2 outside)