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Patent Searching and Data


Title:
SEMICONDUCTOR CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS6392127
Kind Code:
A
Abstract:

PURPOSE: To prevent an overcurrent from flowing through transistors (TR) for an FF even when noises are mixed with a set signal and a reset signal by combining a logic circuit with the FF.

CONSTITUTION: An OR circuit 3 and an AND circuit 4 are combined with a pnp TR1 and an npn TR2 to obtain an FF function. Then even if a noise 5 is mixed with a reset signal R in a set state and R=H holds, a signal V2 is still at 'L' in this period 6 and the TR2 is still off. Even if a noise 7 is mixed with the set signal, the inverse of S in a reset state and the inverse of S=L holds, the signal V1 is still at 'H' and the TR1 stays off. Therefore, even if noises are mixed with the set and reset signals, the TR1 and TR2 never turn on at the same time.


Inventors:
HOSONO MASAHISA
Application Number:
JP23844786A
Publication Date:
April 22, 1988
Filing Date:
October 06, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K19/082; H03K19/00; H03K19/0948; (IPC1-7): H03K17/16; H03K17/60; H03K19/082
Attorney, Agent or Firm:
Uchihara Shin