Title:
半導体複合装置および半導体複合装置の製造方法
Document Type and Number:
Japanese Patent JP7364010
Kind Code:
B2
Abstract:
A semiconductor composite device includes active elements and passive elements constituting a voltage regulator and disposed in association with a plurality of channels, a load to be supplied with a direct-current voltage regulated by the voltage regulator, and a wiring board electrically connected to the active elements, the passive elements, and the load. A plurality of capacitors disposed in the channels include an integrally formed capacitor array including a plurality of capacitor portions disposed in a plane. The capacitor array includes a plurality of through hole conductors extending through the capacitor array in a direction perpendicular to a mounting surface of the wiring board. At least a part of the capacitor array is positioned to overlap the load when viewed from the mounting surface of the wiring board.
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Inventors:
Tatsuya Kitamura
姫田 ▲高▼志
Takeshi Furukawa
姫田 ▲高▼志
Takeshi Furukawa
Application Number:
JP2022176347A
Publication Date:
October 18, 2023
Filing Date:
November 02, 2022
Export Citation:
Assignee:
MURATA MANUFACTURING CO.,LTD.
International Classes:
H05K3/46; H01G2/06; H01G4/38; H01G4/40; H01G9/00; H01G9/012; H01L23/12; H01L25/07; H01L25/18; H02M3/155
Domestic Patent References:
| JP2009518873A | ||||
| JP201330528A | ||||
| JP2016503963A |
Foreign References:
| WO2019130746A1 | ||||
| US20190304915 | ||||
| WO2007129526A1 | ||||
| WO2012101858A1 |
Attorney, Agent or Firm:
Patent Attorney Firm WisePlus
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