To gain a series of access to the internal memory of a CPU indivisibly without being affected by external access by placing a response signal in a state showing that external access to the memory is excluded for a period wherein the CPU gains interlock access.

The processor 100 is equipped with a CPU 110, an internal RAM 120, and a memory controller 160 which controls the interlock access to the internal DRAM 120 by the CPU 110, and the CPU 110 is enabled to gain interlock access. For the purpose, the CPU 110 gains the access indivisibly without being involved in external access to the internal DRAM 120. Therefore, the problem of an access conflict resulting from the one-chip constitution of the internal DRAM 120 and CPU 110 and the internal DRAM 120 can be used as a common memory for the outside. Consequently, interference by external access can be eliminated.