To enable a module requesting data transfer by DMA at the level of a data request signal to use a burst transfer mode in DMA.

When a data request signal is made inactive during data transfer with a burst transfer mode by a DMA controller, an address of that time is held and the remaining number of times of transfer is counted. Re-transfer of the data after the data request signal became inactive is made possible by resetting the address and the remaining number of times of transfer to the DMA controller after the data transfer with the burst transfer mode is finished, to perform the data transfer. By this way, the data transfer using the burst transfer mode is performed to the module requesting the data transfer at the level of the data request signal.