Title:
半導体装置のカウンタ
Document Type and Number:
Japanese Patent JP5015090
Kind Code:
B2
Abstract:
The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in synchronism with a clock signal. The second MUX selects any one of external data and the second output signal of the D-flipflop in response to a data load signal and outputs a selected signal. The first MUX transfers any one of the first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal.
More Like This:
| JPH0691461 | [Title of Invention] Dynamic divider |
| JPS5498654 | ELECTRONIC WATCH |
Inventors:
Hayashi Sogo
Chung
Youn goodness
Chung
Youn goodness
Application Number:
JP2008206663A
Publication Date:
August 29, 2012
Filing Date:
August 11, 2008
Export Citation:
Assignee:
SK hynix Inc.
International Classes:
H03K23/00; H03K23/40
Domestic Patent References:
| JP2008305947A | ||||
| JP2000243041A | ||||
| JP2000132921A | ||||
| JP2000200467A |
Foreign References:
| WO2005027112A1 | ||||
| US20020194548 | ||||
| US20030154434 | ||||
| US20070075732 | ||||
| US20070198101 |
Attorney, Agent or Firm:
Nakagawa International Patent Office