Title:
SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING DEVICE
Document Type and Number:
Japanese Patent JP2016051326
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a technique that enables a semiconductor device for making interaction model computation to perform interaction computation using a three or more-valued coefficient.SOLUTION: A semiconductor device includes a plurality of units, each having; a first memory cell that stores a value representing a state of one node in an interaction model; a second memory cell that stores an interaction coefficient representing an interaction from another node connected to the one node; and a third memory cell that stores a bias coefficient of the one node. The semiconductor device also has an arithmetic circuit that determines a value that represents a next state of the one node on the basis of a value representing a state of the node connected to the one node, the interaction coefficient and the bias coefficient. The second memory cell and the third memory cell of each of the plurality of units include multi-valued memory cells.SELECTED DRAWING: Figure 6
Inventors:
YAMAOKA MASANAO
YOSHIMURA CHIHIRO
YOSHIMURA CHIHIRO
Application Number:
JP2014176238A
Publication Date:
April 11, 2016
Filing Date:
August 29, 2014
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06F7/00; G06F7/49; G06N99/00
Domestic Patent References:
| JP2014075065A | 2014-04-24 | |||
| JP2011524026A | 2011-08-25 |
Other References:
YOSHIMURA CHIHIRO 他: "Spatial computing architecture using randomness of memory cell stability under voltage control", EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), 2013, JPN6015048753, 12 September 2013 (2013-09-12), pages 1 - 4, XP055272708, ISSN: 0003261835, DOI: 10.1109/ECCTD.2013.6662276
Attorney, Agent or Firm:
Yamato Tsutsui