To prevent the lowering of breakdown voltage of a high breakdown voltage system MOS transistor accompanying a thin film of a gate electrode for miniaturization in a semiconductor integrated circuit device, where a logic system MOS transistor and the high breakdown voltage system MOS transistor are mixed-loaded on the same substrate.
The high breakdown voltage system MOS transistor 31 has a thick film gate electrode 33 thicker than a thin film gate electrode 23 of a logic system MOS transistor 21, for example. There is provided a thick film gate side wall insulating film 34 having a side wall length in response to the film thickness of the thick film gate electrode 33 on a side wall of the thick film gate electrode 33. Further, the high withstand voltage system MOS transistor 31 has an LDD structure 35 having an LDD length in response to the side wall length of the thick film gate side wall insulating film 34.
ISOBE KAZUAKI
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto