PURPOSE: To obtain a logical circuit in a high-speed and low power consumption, by forming the composite elements of horizontal pnp-transistors for injection doubling as load and electrostatic induction transistors and also a vertical npn-transistor in shapes that are mutually separated on the same semiconductor substrate.

CONSTITUTION: Two n+-type buried layers 41 are mounted onto a p-type substrate 40, and n-type epitaxial layers 42 with low concentration are grown. Element isolation regions are made up by means of p-type separation walls 43, and n-type conductive passages 44 are installed to each buried layer. A p--type base 45 of a vertical npn-transistor is built up to one n-type island, and p-type regions 46 functioning as the gates of electrostatic induction transistors doubling as the emitters and collectors of horizontal pnp-transistors are formed to the other island. An n-type emitter of the vertical transistor and an n+-type region 47 acting as a drain of the electrostatic induction transistors are simultaneously made up to the both islands. Elements may be isolated by V-shaped grooves by means of aeolotropy etching or polycrystals selectively grown. The buried layers are built up by means of ion injection or diffusion.