Title:
SEMICONDUCTOR DEVICE, MANUFACTURING AND DESIGNING METHOD THEREFOR
Document Type and Number:
Japanese Patent JP2002208676
Kind Code:
A
Abstract:
To improve planarity further for a boundary part of a chip, when planarity process in a CMP method is used.
In the semiconductor device, a dummy pattern 2b made of the same material as a wiring pattern 1 is formed inside a dicing part at a chip boundary part in a prescribed hierarchy out of laminated hierarchies on a semiconductor substrate is formed inside a dicing part. The area of the dummy pattern 2b with to respect the total area of the flat region is made 50% or larger in area constituted by the inner edge of the dummy pattern 2b, the outer edge line of the dicing part, and two desired parallel lines.
Inventors:
SHINKAWADA HIROKI
Application Number:
JP2001002331A
Publication Date:
July 26, 2002
Filing Date:
January 10, 2001
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L23/52; H01L21/304; H01L21/3105; H01L21/3205; H01L21/822; H01L23/528; H01L27/02; H01L27/04; (IPC1-7): H01L27/04; H01L21/3205; H01L21/822
Attorney, Agent or Firm:
Mamoru Takada (3 outside)
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