SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Japanese Patent JP3878781

B2

PROBLEM TO BE SOLVED: To improve reliability in connection in the mounting of a semiconductor device and to facilitate process control during the manufacturing process for a semiconductor device.
SOLUTION: A table which supports a semiconductor chip 2, a sealing body 3 so formed as to resin-seal the semiconductor chip 2, plural of leads 1a which comprise a copper alloy and are exposed on a backside 3a of the sealing body 3, while a solder plating layer 8 is formed on an exposed surface 1d to be mounted to, and a wire 4 which connects a pad 2a of the semiconductor chip 2 to the lead 1a corresponding to it, are provided. The backside 3a of the sealing body 3 is polished with a brush after resin-molding in a manufacturing process, so that with both edge parts, in the width direction being, exposed from the backside 3a of the sealing body 3 of the lead 1a as a bent surface, the central part of the surface 1d of the lead 1a comprising the bent surface is allowed to protrude above the backside 3a of the sealing body 3, for improved connection reliability in mounting.

Takao Matsuura
Yoshihiko Yamaguchi
Kobayashi Noboru
Koji Tsuchiya

JP37126099A

February 07, 2007

December 27, 1999

Click for automatic bibliography generation  

Renesas Technology Corp.
Renesas Northern Japan Semiconductor Co., Ltd.

H01L23/12; H01L21/301; H01L23/50; H01L21/48; H01L21/56; H01L23/31; H01L23/48; (IPC1-7): H01L23/50; H01L21/56; H01L23/12

JP59158528A
JP11016930A
JP11195743A
JP11354705A

Yamato Tsutsui

Previous Patent: INDICATING DEVICE FOR FASTENING PIPE JOINT

Next Patent: FOOD CONDITION EVALUATING METHOD AND DEVICE THEREFOR