SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Title:

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Document Type and Number:

Japanese Patent JP2005175193

Kind Code:

A

Abstract:

To provide a semiconductor device utilizing the electrode of a capacitive element as wiring or a resistor wherein the capacitive coupling between the lower electrode and the upper electrode is suppressed without increasing the height of the capacitive element.

The semiconductor device has a structure wherein a silicon oxide film 3 is embedded within a first groove 2 as an element isolation region in a p-type silicon substrate 1, and an n-type polycrystalline silicon resistor 6 is embedded within a second groove 5 further formed in that silicon oxide film 3. The second groove 5 is not completely filled up with the polycrystalline silicon resistor 6 and has a recess in the surface thereof, and an insulating layer 7 is formed in the recess so that the surface of the insulating layer 7 and the surface of the substrate 1 are held at the same level. Further, an upper electrode of a polycide structure is formed to form the capacitive element together with the polysilicon resistor 6 and a capacitive insulating film 10.

Inventors:

SHIMAZAKI TOYOYUKI

Application Number:

JP2003413004A

Publication Date:

June 30, 2005

Filing Date:

December 11, 2003

Export Citation:

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Assignee:

MATSUSHITA ELECTRIC IND CO LTD

International Classes:

H01L23/52; H01L21/3205; H01L21/822; H01L21/8242; H01L27/04; H01L27/108; (IPC1-7): H01L21/822; H01L21/3205; H01L21/8242; H01L27/04; H01L27/108

Attorney, Agent or Firm:

Fumio Iwahashi
Tomoyasu Sakaguchi
Hiroki Naito

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