To form a transistor using element isolation technique such as STI, current characteristics of the transistor being superior and characteristic variance depending upon its layout being suppressed.

A semiconductor device has an active region 2 of the transistor formed on a surface portion of a semiconductor substrate 1 and an element isolation region 3 in a periphery of the active region 2, a gate electrode 6 formed on the active region 2, a recess region 4 formed by digging from a surface of the active region 2 on the boundary with the element isolation region 3, and an insulating film buried in the recess region 4.