Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP3851752
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a highly-integrated semiconductor device which comprises a heat-resistant gate electrode and a shortened interval between the gate of a metal gate transistor and a source/drain contact.
SOLUTION: There are provided a semiconductor substrate (11), an insulating film (12) and a gate electrode (15) provided on the semiconductor substrate, a source/drain region (53) formed at the semiconductor substrate, and the a metal oxide layer (19) selectively formed on the gate electrode. The gate electrode comprises a first metal while the metal oxide layer comprises a second metal where gibbs standard free energy is reduced more than the first metal at the formation of oxide.
Inventors:
Kyoichi Suguro
Application Number:
JP2000087404A
Publication Date:
November 29, 2006
Filing Date:
March 27, 2000
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/283; H01L29/78; H01L21/265; H01L21/28; H01L21/336; H01L21/768; H01L23/522; H01L29/423; H01L29/43; H01L29/49; H01L29/51; (IPC1-7): H01L29/78; H01L21/283; H01L21/768; H01L29/43
Domestic Patent References:
| JP11224947A | ||||
| JP58028872A | ||||
| JP2000031474A | ||||
| JP1231351A | ||||
| JP7297186A | ||||
| JP11054458A | ||||
| JP6097164A | ||||
| JP6177128A | ||||
| JP11186273A |
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Sadao Muramatsu
Ryo Hashimoto