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Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2011233765
Kind Code:
A
Abstract:

To provide a semiconductor device with its occupied area reduced by employing a three-dimensional capacitor structure while suppressing an increase in leakage current due to a capacitor structure of a compensation capacitive element.

A semiconductor device 20 comprises a crown type capacitor 21a formed in a memory cell region and a concave type compensation capacitive element 10 formed in a peripheral circuit region. A manufacturing method of the semiconductor device 20 comprises a step of forming pads 47a and 47b on a first interlayer insulation film, a step of forming lower electrodes 66a and 66b with a bottomed cylindrical shape on the pads 47a and 47b, a step of covering internal and external wall surfaces of the lower electrode 66a in the memory cell region and only an internal wall surface of the lower electrode 66b in the peripheral circuit region with dielectric films 67a and 67b, and a step of forming upper electrodes 69a and 69b on the dielectric films.


Inventors:
NAKAMURA YOSHITAKA
YAMAZAKI YASUSHI
Application Number:
JP2010103858A
Publication Date:
November 17, 2011
Filing Date:
April 28, 2010
Export Citation:
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Assignee:
ELPIDA MEMORY INC
International Classes:
H01L27/10; H01L21/822; H01L21/8242; H01L27/04; H01L27/108
Domestic Patent References:
JP2009253208A2009-10-29
JP2002009174A2002-01-11
JP2008021698A2008-01-31
JP2002083880A2002-03-22
JP2010067661A2010-03-25
JP2002134506A2002-05-10
Attorney, Agent or Firm:
Sumio Tanai
Tadashi Takahashi
Naoki Ofusa
Kazunori Onami



 
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