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Title:
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Document Type and Number:
Japanese Patent JP2011049282
Kind Code:
A
Abstract:

To form a low voltage MISFET of high performance, and a highly reliable MONOS type nonvolatile memory and a high voltage MISFET.

A silicide is prevented from being formed on a dummy gate electrode by using a cap oxide film as a mask, in a forming area of the low voltage MISFET used in a logic circuit or the like, and a forming step is simplified when forming a gate of the low voltage MISFET using a damascene process by a high-k film 18 and a metal gate electrode 20. The reliability of an element is secured by removing once a gate insulating film damaged by an RIE when removing the dummy gate electrode, and by forming newly a gate oxide film 17.


Inventors:
YAMABE KAZUHARU
TANIGUCHI YASUHIRO
YOSHIDA SEIJI
KANBARA SHIRO
KUMIHASHI KOSEI
Application Number:
JP2009195360A
Publication Date:
March 10, 2011
Filing Date:
August 26, 2009
Export Citation:
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Assignee:
RENESAS ELECTRONICS CORP
International Classes:
H01L27/115; H01L21/336; H01L21/768; H01L21/8234; H01L21/8247; H01L23/522; H01L27/088; H01L29/78; H01L29/788; H01L29/792
Domestic Patent References:
JP2000307010A2000-11-02
JP2006060173A2006-03-02
JP2001291867A2001-10-19
JP2007234861A2007-09-13
JP2009016706A2009-01-22
JP2002222876A2002-08-09
JP2007234861A2007-09-13
JP2009016706A2009-01-22
JP2002222876A2002-08-09
JP2000307010A2000-11-02
JP2006060173A2006-03-02
JP2001291867A2001-10-19
JP2007067027A2007-03-15
JP2003282743A2003-10-03
JP2004349680A2004-12-09
Attorney, Agent or Firm:
Yamato Tsutsui



 
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