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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2004055812
Kind Code:
A
Abstract:

To improve characteristics of a device by lowering the gate resistance of a power MISFET.

A gate electrode GE is electrically connected with a gate formed of a polycrystalline silicon film inside a plurality of grooves formed in stripe shaper in the Y direction of a chip area CA. The gate electrode GE is formed of a film in the same layer as a source electrode SE electrically connected to a source region formed between the stripe grooves. Moreover, the gate electrode GE comprises a gate electrode G1 formed along the periphery of the chip area CA, and a gate finger G2 so located as to divide the chip region CA into two parts in the X direction. Meanwhile, the source electrode SE comprises a portion located above the gate finger G2 and a portion located below the gate finger G2. The gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.


Inventors:
SHIRAI NOBUYUKI
MATSUURA NOBUYOSHI
Application Number:
JP2002211019A
Publication Date:
February 19, 2004
Filing Date:
July 19, 2002
Export Citation:
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Assignee:
RENESAS TECH CORP
International Classes:
H01L21/336; H01L21/60; H01L23/482; H01L29/417; H01L23/495; H01L23/544; H01L29/76; H01L29/78; (IPC1-7): H01L29/78; H01L21/60; H01L29/417
Domestic Patent References:
JPH0334467A1991-02-14
JPH10163483A1998-06-19
JP2004502293A2004-01-22
JPH08181307A1996-07-12
JPH08340029A1996-12-24
JPS63249346A1988-10-17
Foreign References:
WO2001059842A12001-08-16
Attorney, Agent or Firm:
Yamato Tsutsui



 
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