To provide a semiconductor device capable of apparently increasing a time usable for computing in combinational circuits and of inspecting both of setup time errors and hold time errors.

The semiconductor device includes a first latch 112, a second latch 113 connected in parallel with the first latch for inputting output data of data treatment circuits, a first clock controller 115 supplying a reference clock clk and a second clock clk- with a phase put forward from the reference clock, a first comparator 114 comparing latch data of the first latch and latch data of the second latch and generating an error signal depending on the comparison result, and a controller 170; in which the first latch 112 synchronizes with the second clock and latches the input data and outputs the latch data to a data pass and the comparator, and the second latch 113 synchronizes with the reference clock and latches the input data and outputs the latch data to the comparator 114.