Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2015222612
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a cache memory having a valid bit, which is capable of performing an invalidation process at high speed by devising a circuit configuration in a memory cell of the valid bit.SOLUTION: The present invention relates to a memory cell of a valid bit configured such that two inverters are connected in series to form a loop, a drain of an N-type transistor 214A is connected to an output node 211B of any one of the inverters, a gate is connected to a reset signal (line 215A) of a CPU, and a source is connected with a ground line 206, where an initial value of the memory cell is determined by inputting a reset signal of the CPU to the gate.
Inventors:
FUJITA MASAFUMI
KUROKAWA YOSHIMOTO
KUROKAWA YOSHIMOTO
Application Number:
JP2015153281A
Publication Date:
December 10, 2015
Filing Date:
August 03, 2015
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB
International Classes:
G11C11/413; G11C11/412
Domestic Patent References:
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Foreign References:
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