Title:
半導体装置
Document Type and Number:
Japanese Patent JP4744849
Kind Code:
B2
Abstract:
A semiconductor device having a surface MEMS element, includes a semiconductor substrate, and an actuator which is arranged above the semiconductor substrate via a space and has a lower electrode, an upper electrode, and a piezoelectric layer sandwiched between the lower electrode and the upper electrode, at least an entire surface of the piezoelectric layer being substantially flat.
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Inventors:
Tatsuya Oguro
Shuichi Sekine
Tamio Ikehashi
Mie Matsuo
Shuichi Sekine
Tamio Ikehashi
Mie Matsuo
Application Number:
JP2004327727A
Publication Date:
August 10, 2011
Filing Date:
November 11, 2004
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L41/08; H01H57/00; H01L21/329; H01L21/822; H01L21/8234; H01L21/8246; H01L27/04; H01L27/06; H01L27/105; H01L29/93; H01L41/09; H01L41/18; H01L41/187; H01L41/193; H01L41/22; H01L41/311; H04R17/00
Domestic Patent References:
| JP6120416A | ||||
| JP6029741A | ||||
| JP63120481A | ||||
| JP60211986A | ||||
| JP2004127973A | ||||
| JP2000031397A |
Attorney, Agent or Firm:
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto