Title:
Semiconductor device
Document Type and Number:
Japanese Patent JP6066658
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To allow a plurality of integrated circuits to be easily laminated, and to improve mounting efficiency without decreasing the degree of freedom of layout of each integrated circuit.SOLUTION: A connection region 108 for connecting a bottom layer LSI103 and a top layer LSI107 is arranged between the LSI103 and LSI107. The area of an LSI106 is smaller than the area of the LSI103 and the area of the LSI107, and the connection region is arranged so as to overlap with a part of the LSI103 and the LSI107.
Inventors:
Kimio Shiozawa
Koichi Sasaki
Koichi Sasaki
Application Number:
JP2012229823A
Publication Date:
January 25, 2017
Filing Date:
October 17, 2012
Export Citation:
Assignee:
Canon Inc
International Classes:
H01L25/065; H01L25/07; H01L25/18; H01L27/10; H01L27/14
Domestic Patent References:
| JP2006086150A | ||||
| JP2012156186A | ||||
| JP2008159607A | ||||
| JP5121713A |
Attorney, Agent or Firm:
Another role Shigehisa
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