Title:
Semiconductor device
Document Type and Number:
Japanese Patent JP6111984
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device which incorporates a capacitor Cgs and a gate resistance Rg or only the capacitor Cgs in order to prevent erroneous turning-on.SOLUTION: In a semiconductor device incorporating a MOSFET and reflux diode, a capacitance value Cgso(nF) of a capacitor connected between a gate and a source of the MOSFET, a resistance value Rgo(Ω) of gate resistance connected to the gate and an inductance value Lgo(nH) of the gate are determined within a range which satisfies the following formula. However, the capacitor and the gate resistance are housed in a resin case. [Formula 1] Cgso>22×(Lgo/2.5)×exp(-0.18×Rgo)+0.025×Rgo×(Lgo/2.5)where Cgso is within a range of 2 nF-20 nF, Rgo is within a range of 3 Ω-20 Ω and Lgo is within a range of 2.5 nH-10 nH.
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Inventors:
Nakano Hito
Application Number:
JP2013233681A
Publication Date:
April 12, 2017
Filing Date:
November 12, 2013
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H02M1/08; H01L25/07; H01L25/18; H03K17/16; H03K17/695
Domestic Patent References:
| JP201399133A | ||||
| JP201313220A | ||||
| JP8204065A | ||||
| JP2000243905A |
Attorney, Agent or Firm:
Akira Sakamoto