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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH01289264
Kind Code:
A
Abstract:

PURPOSE: To reduce the complexity when a pattern is designed and manufactured by a method wherein trenches for element isolation use are arranged in advance in a lattice shape.

CONSTITUTION: When a circuit is designed, an element formation region 2 separated by trenches 1 arranged in advance in a lattice shape is selected and designed, a size of the element formation region 2 is set to a size of a smallest element and, when elements of different sizes are arranged, one part 3 of the trenches 1 is removed. The trenches in regions where the element is not formed are left as they are. By this setup, when the circuit is designed, it is not required to consider an interval between one trench and the other trench. It is not required to consider a change in etching rate during a reactive etching operation for formation of a groove it is possible to reduce the complexity when an integrated circuit is designed and manufactured.


Inventors:
HIRAKAWA KENJI
Application Number:
JP11830488A
Publication Date:
November 21, 1989
Filing Date:
May 17, 1988
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L29/73; H01L21/02; H01L21/331; H01L21/76; H01L21/763; H01L21/8222; H01L27/06; H01L29/732; (IPC1-7): H01L21/76; H01L27/06; H01L29/72
Attorney, Agent or Firm:
Norio Ohu