PURPOSE: To reduce the complexity when a pattern is designed and manufactured by a method wherein trenches for element isolation use are arranged in advance in a lattice shape.
CONSTITUTION: When a circuit is designed, an element formation region 2 separated by trenches 1 arranged in advance in a lattice shape is selected and designed, a size of the element formation region 2 is set to a size of a smallest element and, when elements of different sizes are arranged, one part 3 of the trenches 1 is removed. The trenches in regions where the element is not formed are left as they are. By this setup, when the circuit is designed, it is not required to consider an interval between one trench and the other trench. It is not required to consider a change in etching rate during a reactive etching operation for formation of a groove it is possible to reduce the complexity when an integrated circuit is designed and manufactured.
JPS59158556 | MANUFACTURE OF P-N-P TRANSISTOR |
JPH027529 | BIPOLAR TRANSISTOR AND ITS MANUFACTURE |
Next Patent: DIVIDING OF SUBSTRATE