PURPOSE: To ensure a stable counting operation by eliminating the timing error caused by the increase of the speed a system clock and also eliminating the delay of a latter half part caused by the parasitic capacity.

CONSTITUTION: A system clock is connected to the clock input of a flip-flop 12, and the clock inputs of the flip-flop 13, 14 and 16 are connected to the Q output of the flip-flop of the precedent stage. The clock input of a flip-flop 15 is connected to the inverted output NQ of the flip-flop of the precedent stage. Furthermore the reset signals are applied to the flip-flops with the output of the decoder consisting of an inverter circuit 17, the NAND circuits 18 and 19, and a NOR circuit 20. The delay of a latter half part is absorbed by the flip-flop of a first half part when the output of the flip-flop 15 varies earlier by a half cycle. Thus a semiconductor device can ensure a stable counting operation.