Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH07202141
Kind Code:
A
Abstract:
PURPOSE: To provide a semiconductor device which is excellent in latch-up resistance by a method wherein the device is improved in breakdown strength between wells.
CONSTITUTION: Impurities are introduced into a P-type semiconductor substrate 1 up to 1×1015cm-3 or so in concentration. An N-type well region 3 and a P-type well region 5 are formed on the surface of the P-type semiconductor substrate. N-type impurities are introduced into the N-type well region 3 up to 1×1016cm-3 or so in concentration, and P-type impurities are introduced into the P-type well region 5 up to a concentration of 1×1016cm-3 or so. The N-type well region 3 and the P-type well region 5 are provided apart from each other by a distance of 2.0μm.
Inventors:
AJIKA NATSUO
Application Number:
JP41094A
Publication Date:
August 04, 1995
Filing Date:
January 07, 1994
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/8247; H01L27/115; (IPC1-7): H01L27/115
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)