Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5988832
Kind Code:
A
Abstract:
PURPOSE:To prevent the lowering of reliability and characteristics of a micro- miniaturized device by arranging a fault deposition layer and a faultless deposition layer within a semiconductor substrate as well as by arranging a potential barrier in a partial region located more deeply than elements of the faultless deposition layer. CONSTITUTION:In a p-n junction barrier provided with P layer in a faultless deposition layer arranged in n- or pi-type substrate, a potential well EB is produced on a valence band Ev and positive carriers are prevented from diffusing into an element forming region at surface. Accordingly, a width of the faultless deposit is narrowed and the fault deposit is brought to be extreamly close to the element forming region up to 1mum to said region, thereby preventing alpha-ray interference or carrier injection efficiently and improving reliability. For the potential barrier EB, p-n-p or n-p-n junction or of the same conductive type layers having different concentrations may be adopted. When depths of the elements are different to each other, a potential barrier is arranged to enclose an element layer and also arranging a potential barrier only on the upper surface of a fault deposition layer as shown in the figure by a solid line is sufficient enough.
Inventors:
IMAOKA KAZUNORI
Application Number:
JP19927882A
Publication Date:
May 22, 1984
Filing Date:
November 12, 1982
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L21/322; (IPC1-7): H01L21/322
Domestic Patent References:
| JPS57107074A | 1982-07-03 |
Attorney, Agent or Firm:
Sadaichi Igita