Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6020521
Kind Code:
A
Abstract:
PURPOSE:To obtain a wiring, dimensional accuracy thereof is high and resistance thereof is low, by forming the wiring on a package substrate by a multilayer wiring consisting of chromium and copper. CONSTITUTION:A wiring 4 is formed as three layer thin-film multilayer wirings consisting of a chromium layer 10 formed on a package substrate 1 after sintering through the evaporation of a thin-film, a copper layer 11 evaporated on the layer 10 in a thin-film shape and a chromium layer 12 evaporated on the layer 11 in the thin-film shape. A pedestal section 5 is composed of a copper layer 13 evaporated on the chromium layer 12 as the uppermost layer of the wiring 4 in the thin-film shape and a chromium layer 14 evaporated around the copper layer 13 in the thin-film shape. Since the wiring 4 is formed by the three layer thin- film evaporated layers of the chromium layer 10, the copper layer 11 and the chromium layer 12, the wiring 4 and the pedestal section 5 are formed with dimensional accuracy higher than a tungsten wiring formed through sintering. Accordingly, a large-sized pellet can be face-down bonded, and the resistance of the wiring 4 can be lowered by the presence of the copper layer 11.
Inventors:
ISHIDA TAKASHI
SEKI MASATOSHI
SAWARA KUNIZOU
EMOTO YOSHIAKI
KAMATA CHIYOSHI
SEKI MASATOSHI
SAWARA KUNIZOU
EMOTO YOSHIAKI
KAMATA CHIYOSHI
Application Number:
JP12763083A
Publication Date:
February 01, 1985
Filing Date:
July 15, 1983
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H01L21/60; (IPC1-7): H01L23/48
Attorney, Agent or Firm:
Yamato Tsutsui
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