Title:
A manufacturing method and a semiconductor device of a semiconductor chip with an adhesives layer
Document Type and Number:
Japanese Patent JP6020520
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor chip with a thin adhesive layer, capable of miniaturizing a semiconductor device.SOLUTION: The method of manufacturing a semiconductor chip with an adhesive layer comprises: a coating step of applying an adhesive composition containing a solvent onto one surface of a semiconductor wafer having a circuit on the other surface; an adhesive layer forming step of removing the solvent in the adhesive composition to form an adhesive layer; and a cutting step of cutting the semiconductor wafer having the adhesive layer formed thereon to obtain a semiconductor chip with the adhesive layer. The adhesive composition contains (A) a thermoplastic resin, (B) a thermosetting resin, (C) the solvent removable by heating, and an inorganic filler. The content of the inorganic filler is 1-1,000 pts.mass based on 100 pts.mass of the thermoplastic resin (A).
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Inventors:
Takashi Kawamori
Mitsukura
Takashi Masuko
Katogi Shigeki
Shinjiro Fujii
Mitsukura
Takashi Masuko
Katogi Shigeki
Shinjiro Fujii
Application Number:
JP2014143602A
Publication Date:
November 02, 2016
Filing Date:
July 11, 2014
Export Citation:
Assignee:
Hitachi Chemical Co., Ltd.
International Classes:
H01L21/52; C09J11/04; C09J179/08; C09J201/00
Domestic Patent References:
| JP2008201998A | ||||
| JP2009152493A | ||||
| JP2007103954A | ||||
| JP2008124233A | ||||
| JP2008288571A | ||||
| JP2006100784A |
Attorney, Agent or Firm:
Yoshiki Hasegawa
Yoshinori Shimizu
Tomoya Furoshita
Yasunori Ishizaka
Yoshinori Shimizu
Tomoya Furoshita
Yasunori Ishizaka