Title:
半導体装置および半導体装置の製造方法
Document Type and Number:
Japanese Patent JP7044653
Kind Code:
B2
Abstract:
The semiconductor device 80 of the present invention includes: a wiring layer 22; a first semiconductor chip 25 that connects the main surface to the wiring layer 22 through a first connection part 28; a plurality of conductive binding posts 24 allocated on the outer side of the semiconductor chip 25 in a bird's eye view, and extending in a direction perpendicular to the wiring layer 22; a thermally conductive member 30 connected to the back surface of the first semiconductor chip 25 opposite to the main surface and at least one of the plurality of conductive binding posts 24 (24G); a sealing resin 29 in contact with the surface other than the back surface of the first semiconductor chip 25, the wiring layer 22, and the side surface of the conductive binding posts 24; and a second semiconductor chip 125 connected to the end parts of the conductive binding posts 24 opposite to the wiring layer 22 through the second connection part 71.
Inventors:
Shinji Wakisaka
Ichiro Kono
Osamu Okada
Masato Fukushima
Ichiro Kono
Osamu Okada
Masato Fukushima
Application Number:
JP2018132564A
Publication Date:
March 30, 2022
Filing Date:
July 12, 2018
Export Citation:
Assignee:
Aoi Electronics Co., Ltd.
International Classes:
H01L25/10; H01L23/12; H01L23/36; H01L25/11; H01L25/18; H05K1/02; H05K3/46
Domestic Patent References:
| JP2002343904A | ||||
| JP2013182974A | ||||
| JP2006080521A | ||||
| JP2009070882A | ||||
| JP2015195368A | ||||
| JP2010245269A |
Foreign References:
| KR1020180020849A |
Attorney, Agent or Firm:
Asuko Sudo
Akinobu Sudo
Akinobu Sudo
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