PURPOSE: To enable judging of a deficiency data and a defective location in a short time by setting a circuit which allows the outputting from memories divided in a proper number simultaneously to judge outputs simultaneously utilizing pins used or unused of a semiconductor.

CONSTITUTION: This apparatus is provided with a test mode control circuit 6-a to control a writing and a reading of numerous signals simultaneously at a timing in a test mode, a test mode control circuit 6-b to switch a normal output to a simultaneous numerous output and an input buffer 8 at a timing in the test mode. When, a signal 7 for test mode is applied, a numerous input/ output mode is entered, the setting of an address, a data input and a data output are switched under a control of the circuit 6-a and data are read simultaneously from blocks of a memory cell block 1 to be checked. This enables the checking of a memory data in a short time while allowing the spotting of a defective address with little changing of a port and an output pad 4.