To realize a semiconductor IC circuit which can check a SAMPLE mode function of a boundary scan register without preparing a test pattern with an internal logic circuit.

A boundary scan register comprises a selector 1 to select either one of a SAMPLE mode function checking data DS prescribed by IEEEStd. 1149.1 or a parallel input PI of an internal logic circuit and a selector 2 which inputs an output of the selector 1 and a scan output data of a front stage boundary scan register to select and output either one thereof. A flip flop 3 is provided to output a data synchronizing a clock signal T1, a flip flop 4 to output a data synchronizing a clock signal T2 and a selector 5 to select and output either one of an output of the flip flop 4 or an output of the selector 1.