Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND INFORMATION PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JP3687875
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To automatically set a desired logic threshold voltage with low power consumption.
SOLUTION: An input Vin1 is added to a common gate of a PMOSFETMp1 and an NMOSFETMn1 and is outputted to an inverter G1. Three pieces NMOSMn2 to Mn4 are connected in parallel between the Mn1 and a ground, and the conductance of the Mn1 is taken so that it may be larger than the conductance of the Mn2 to the Mn4. Also, the Mn2 is stationarily tuned on, control signals C0 and C1 are added to the gates of the Mn3 and the Mn4, and on-off control is performed. A logic threshold voltage is decided by the ratio of the conductance of the Mp1 and a composite conductance of plural Mns, and a desired threshold voltage is acquired by controlling the Mns with a control signal.
Inventors:
Toshiro Takahashi
Application Number:
JP31422496A
Publication Date:
August 24, 2005
Filing Date:
November 11, 1996
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H03K19/003; H03K19/0175; (IPC1-7): H03K19/0175; H03K19/003
Domestic Patent References:
| JP5268054A | ||||
| JP4134923A | ||||
| JP6112806A | ||||
| JP1503510A | ||||
| JP4104611A |
Attorney, Agent or Firm:
Mitsumasa Tokuwaka