To provide an ESD protection circuit that allows an ESD protection element to protect the ESD of an internal element while securing sufficient ESD breakdown strength and also reduces an area, in a power management semiconductor device having a fully depleted SOI device structure and in an analog semiconductor device.

The device has such a structure that uses an NMOS protection transistor formed on an SOI semiconductor thin film layer as an ESD protection device at an output terminal of an internal element, particularly an NMOS transistor, of fully depleted SOI MOS formed on the semiconductor thin film layer, while using the NMOS protection transistor formed on a semiconductor supporting substrate, to precedently absorb the noise of the ESD, to protect an input and an output of the internal element on the semiconductor thin film that is weak to the noise of the ESD, and to reduce an area of a protection circuit, while securing ESD breakdown strength.