To provide a semiconductor integrated circuit device with small noise sensitivity capable of suppressing a sampling dependent period of a sampling/hold error to a small value and realizing a highly accurate and stable sampling/hold.
At a sample/hold circuit 9, resistors 10 and 11 are connected to both assistant joints of a transistor 12, respectively, and a capacitor 13 is connected between a joint of another side of the resistor 11 and standard potential VSS. Since the resistors 10 and 11 are connected to both joints of the transistor 12 respectively as described, both of an input signal Vin side and a capacitor 13 side have a time constant of (Cg(: back gate capacity of the transistor 12)/2R) during extraction and insertion of electron charge when the transistor 12 is turned on, and a hold offset voltage Vhoff is set to qg/2Csh.
FUJITA SATOSHI
SAWADAISHI TOMOYUKI
