Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3762856
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To allow acceleration of an operating speed and low power consumption of a CMOS circuit to be compatible.
SOLUTION: Control circuits FRQCNT, VDDCNT and VBBCNT generate an optimum clock signal, power supply voltage and substrate bias in response to an instruction signal CMD of an instruction generator OP, and supplies the signals to a main circuit LSI. Thus, unevenness of CMOS circuit characteristics is suppressed to improve the performance of the circuit. Reduction in power is realized without deteriorating the operating speed of the CMOS circuit or acceleration is realized without increasing the power consumption in the CMOS circuit.
Inventors:
宮▲崎▼ 祐行
Koichiro Ishibashi
Koichiro Ishibashi
Application Number:
JP2000164717A
Publication Date:
April 05, 2006
Filing Date:
May 30, 2000
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L27/04; H03K19/094; G11C11/407; H01L21/822; H01L21/8234; H01L27/088; H03K19/00; H03K19/003; H03K19/0948; H03K19/096; (IPC1-7): H03K19/094; G11C11/407; H01L27/04; H01L21/822; H03K19/0948
Domestic Patent References:
| JP10187270A | ||||
| JP10242840A | ||||
| JP11122047A | ||||
| JP9008645A | ||||
| JP8017183A | ||||
| JP6291267A | ||||
| JP6237164A | ||||
| JP2001156261A |
Foreign References:
| WO1999010796A1 |
Attorney, Agent or Firm:
Shizuyo Tamamura
Yasuo Sakuta
Yasuo Sakuta