PURPOSE: To secure the sufficient holding time for the enable and clock signals which are inputted to a counter circuit of the next stage when a synchronizing counter circuit is constructed with the cascade connection of plural ripple type counter circuits consisting of the macrocell libraries.

CONSTITUTION: A latch circuit 60 is provided between a counter circuit 1 of the precedent stage and a counter circuit 2 of the next stage and latches the signal of a ripple carry terminal RC outputted from the circuit 1. Then the circuit 60 outputs the latched signal in the output timing of the carry terminal MM of the circuit 1 and supplies it to the circuit 2 as an enable signal. Thus the sufficient holding time is secured for both enable and clock signals which are inputted to a T-FF 51-2 included in the circuit 2. Then the accurate operation is secured for the T-FF 51-2.