PURPOSE: To shorten the test time of a semiconductor integrated circuit device provided with a memory and to reduce costs for its test.
CONSTITUTION: A first selector circuit 21 is controlled by a testmode signal S, the signal of an internal circuit is selected in an ordinary operation, and test data is selected in a test operation so as to be written into a memory 22. The operation of the memory is controlled by a memory control circuit 23. The test data which has been read out from the memory and a control signal which is output from the memory control circuit are supplied to a second selector circuit 24, the control signal of the memory control circuit is selected so as to be output from an external output terminal 25 in the write operation of the test data to the memory by the control of a read/write signal R/W which is output from the memory control circuit. While the test data is being written into the memory, the control signal of the memory control circuit is output from the external output terminal so as to be capable of being monitored. As a result, the test time of a semiconductor integrated circuit device can be shortened, and its costs can be lowered.
KONISHI KAZUO
NAKA HIDEYUKI
OISHI KAZUYUKI
