Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP4488800
Kind Code:
B2
Abstract:
Current consumption in a nonvolatile memory apparatus operable on two or more different power voltages is to be substantially reduced in its standby mode. A stepped-down power supply unit provided in a flash memory to generate an internal power voltage, when supplied from outside with about 3.3 V as a power voltage, causes a first stepped-down power supply circuit to output the internal power voltage to control circuits when in normal operation. In a low power consumption mode, a second stepped-down power supply circuit outputs the internal power voltage to the control circuits, and in a standby mode a third stepped-down power supply circuit outputs to the control circuits an internal power voltage stepped down by an N-channel MOS transistor.
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Inventors:
Sakurai Ryotaro
Hideo Chigasaki
Kasai Hideo
Hideo Chigasaki
Kasai Hideo
Application Number:
JP2004174902A
Publication Date:
June 23, 2010
Filing Date:
June 14, 2004
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C16/06; G11C5/14; G11C11/34; G11C11/4074; G11C11/413; G11C16/30
Domestic Patent References:
| JP10214496A | ||||
| JP2002373942A | ||||
| JP4212786A | ||||
| JP2005141811A | ||||
| JP5012890A | ||||
| JP2000101024A | ||||
| JP2000163144A | ||||
| JP63076007A |
Foreign References:
| WO2004025817A1 |
Attorney, Agent or Firm:
Yamato Tsutsui