Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DESIGNING THE SAME
Document Type and Number:
Japanese Patent JP3936133
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce number of kinds of the cells contained in a library.
SOLUTION: A cell containing a plurality of circuit elements each of which is arranged in a specified position and among which specified mutual connections are made is called from a library. Signal application forms to the cell are specified depending on required basic logic functions (NAND and NOR), and mutual wiring among each of a plurality of the cells is determined. For example, if open drain terminals 19 and 21 are grounded and an input signal (C) that is independent from other input signals is applied to a drain terminal 20, a three-input NAND can be formed. If open drain terminals 20 and 21 are connected to a power source and the independent signal is applied to the terminal 19, a three-input NOR can be formed.
Inventors:
Kazuo Yano
Yasuhiko Sasaki
Yasuhiko Sasaki
Application Number:
JP2000340388A
Publication Date:
June 27, 2007
Filing Date:
November 08, 1993
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F17/50; H01L21/82; H01L27/118; H03K19/0944; (IPC1-7): H01L21/82; G06F17/50; H01L27/118; H03K19/0944
Domestic Patent References:
| JP4137651A | ||||
| JP5198672A |
Attorney, Agent or Firm:
Shizuyo Tamamura
Yasuo Sakuta
Yasuo Sakuta
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