SEMICONDUCTOR INTEGRATED CIRCUIT AND VERIFICATION METHOD THEREFOR

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT AND VERIFICATION METHOD THEREFOR

Document Type and Number:

Japanese Patent JP2000269420

Kind Code:

A

Abstract:

To simplify a test for confirming connection between function macros, to simplify the verification of the design of a system LSI and to shorten the design time period of the system LSI in the case of constituting the system LSI by combining the plural pieces of the function macros.

This semiconductor integrated circuit is provided with two pieces of IPs (design properties) 12 and 13 provided with a test circuit for confirming the connection between the IPs via a signal line. The test circuit of one IP 12 is provided with a register 21 activated by an inter-IP connection confirmation test mode for writing test data from an MPU(microprocessor unit) 10 and an output circuit 25, for outputting the test data written in the register to the signal line 20, and the test circuit of the other IP 13 is provided with the register 31 activated by the inter-IP connection confirmation mode, for writing the test data inputted from the signal line and reading the test data to the MPU.

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Inventors:

YAMAZAKI AKIHIRO

Application Number:

JP7570899A

Publication Date:

September 29, 2000

Filing Date:

March 19, 1999

Export Citation:

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Assignee:

TOSHIBA CORP

International Classes:

H01L21/822; H01L27/04; (IPC1-7): H01L27/04; H01L21/822

Attorney, Agent or Firm:

Takehiko Suzue (6 outside)

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