SEMICONDUCTOR INTEGRATED CIRCUIT WITH TEST CIRCUIT AND MANUFACTURE THEREOF

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT WITH TEST CIRCUIT AND MANUFACTURE THEREOF

Document Type and Number:

Japanese Patent JPH0774319

Kind Code:

A

Abstract:

PURPOSE: To conduct the AC characteristic test of an LSI easily and accurately.

CONSTITUTION: An AC characteristic test circuit, which is connected to an output terminal 7 from an input terminal 1 through the intermediary of the gate, which is a plurality groups of buffer circuits formed from an input terminal 1, is provided in an LS 18 in addition to the prescribed functional circuit. An LSI testing machine is connected to the input terminal 1, an input signal is applied, and a clock signal is applied to a clock terminal 2. As a result, a signal waveform, in which the delay time of each gate from the rise of a clock signal, is outputted to an output terminal 7, and the AC characteristics of an LSI 8 is judged by the length of the delay time.

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Inventors:

TAKIZAWA TADASHI

Application Number:

JP22076793A

Publication Date:

March 17, 1995

Filing Date:

September 06, 1993

Export Citation:

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Assignee:

NEC IBARAKI LTD

International Classes:

H01L21/822; H01L27/04; G01R31/28; (IPC1-7): H01L27/04; H01L21/822; G01R31/28

Attorney, Agent or Firm:

Naoki Kyomoto (2 outside)

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