Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2004071083
Kind Code:
A
Abstract:
To reduce the area of a mask ROM, by providing a mechanism which can output both binary logical values from one memory cell, according to the address region and enabling one memory block to be shared in two address region.
The address region allocated to a memory cell array comprises two addresses, that is, the addresses of f0000h and e0000h. The time width in read data is 50 nsec for the address of f0000h and 31 nsec for the address of e0000h. In a short L and wide W (only 2G) memory cell, "H:L" is obtained. In a memory cell with a channel cut, "L:L" is obtained. In a long L and narrow W (only 2G) memory cell, "L:H" is obtained. In a short L and wide W (1G + 2G) memory cell, "H:L" is obtained.
Inventors:
NAGATA SHINYA
Application Number:
JP2002230950A
Publication Date:
March 04, 2004
Filing Date:
August 08, 2002
Export Citation:
Assignee:
RENESAS TECH CORP
International Classes:
G11C17/00; G11C17/18; H01L21/8246; H01L27/112; (IPC1-7): G11C17/00; G11C17/18; H01L21/8246; H01L27/112
Attorney, Agent or Firm:
Hiroaki Sakai