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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2008118004
Kind Code:
A
Abstract:

To provide a semiconductor integrated circuit comprising a MOS transistor which ensures a sufficient LOD and has a desired on current.

This semiconductor integrated circuit is one which comprises a plurality of standard cells disposed adjacently in a first direction on a semiconductor substrate. Each of the standard cells comprises a first diffusion layer 103 connected to a first power supply 101 and a second diffusion layer 104 connected to a second power supply 102, and the first diffusion layers 103 and the second diffusion layers 104 of all the standard cells disposed adjacently are wholly integrated with each other and formed.


Inventors:
NAGAMITSU MASATOMO
SAEKI TAKANORI
Application Number:
JP2006301302A
Publication Date:
May 22, 2008
Filing Date:
November 07, 2006
Export Citation:
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Assignee:
NEC ELECTRONICS CORP
International Classes:
H01L21/82; H01L21/822; H01L27/04
Domestic Patent References:
JPH0541452A1993-02-19
JPH04372168A1992-12-25
JP2004327540A2004-11-18
JPH09289251A1997-11-04
Attorney, Agent or Firm:
Ken Ieiri