Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP4580882
Kind Code:
B2
Abstract:
A semiconductor integrated circuit including: a mixer circuit which includes a first MOS transistor a second MOS transistor; a third MOS transistor whose drain is connected to a first potential, and which has a conductivity type and a threshold value which are the same as those of the first MOS transistor and the second MOS transistor; a current source connected between the source of the third MOS transistor and a second potential; a voltage dividing circuit which is connected between the first potential and the second potential, and divides a voltage between the first potential and the second potential to output a divided voltage as a reference voltage; and a differential amplifier circuit whose in-phase input receives the reference voltage, whose anti-phase input receives a source potential of the third MOS transistor, and whose output is connected to a gate of the third MOS transistor.
Inventors:
Daisuke Miyashita
Application Number:
JP2006065531A
Publication Date:
November 17, 2010
Filing Date:
March 10, 2006
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03D7/00; H03D7/12
Domestic Patent References:
| JP2005184141A | ||||
| JP2002111412A | ||||
| JP2000196363A | ||||
| JP3230605A |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki