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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH01123453
Kind Code:
A
Abstract:

PURPOSE: To select and set simply an input terminal in a pull-up or a pull-down at need by a method wherein the proper use of the pull-up and the pull-down is performed utilizing the 2 states of a CMOS inverter.

CONSTITUTION: An input terminal 2 of an input circuit 1 constituted of two stages of inverters is connected to an output node of a CMOS inverter 10 provided with a P-channel pull-up transistor Qa and an N-channel pull-down transistor Qb. When a selective control terminal 3 is fixed in a state that a selective control voltage at an 'L' level is applied to the terminal 3, the Qa is turned on, the Qb is turned off and the terminal 2 is pulled up by the on resistance of the Qa. Contrast to this, in case the terminal 3 is fixed in a state that a selective control voltage at an 'H' level is applied to the terminal 3, the Qa is turned off, the Qb is also turned on and the terminal 2 is pulled down by the on resistance of the Qb.


Inventors:
SUGINO HIROYUKI
SHICHINOHE DAISUKE
Application Number:
JP28172387A
Publication Date:
May 16, 1989
Filing Date:
November 07, 1987
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L27/04; H01L21/822; H01L27/118; (IPC1-7): H01L27/04
Domestic Patent References:
JPS61173514A1986-08-05
Attorney, Agent or Firm:
Shigeaki Yoshida (2 outside)