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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH05259893
Kind Code:
A
Abstract:

PURPOSE: To attain high circuit integration and to quicken the operation by allowing a CMOS dynamic semiconductor integrated circuit to prevent malfunction due to a leak current and malfunction in the cascode connection even without an inverter.

CONSTITUTION: The circuit is provided with MOS transistors(TRs) 2, 3 whose gates and drains are in cross connection for an output latch and with MOS TRs 4, 5 for output precharge. Since the MOS TR 1 is turned off, the MOS TRs 4, 5 are turned on when a clock signal CLK is at a low level, outputs Q, inverse of Q are precharged to a high level. When the clock signal CLK changes to a high level, the MOS TR 1 is turned on and the MOS TRs 4, 5 are turned off. In this case, one of MOS TR groups makes the output and a GND potential conductive to set an output potential to a low level depending on the state of input signals IN and inverse of IN.


Inventors:
Katsuya Furuki
Application Number:
JP5686791A
Publication Date:
October 08, 1993
Filing Date:
March 20, 1991
Export Citation:
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Assignee:
NEC
International Classes:
H03K19/096; G11C11/408; H03K3/356; (IPC1-7): H03K19/096
Attorney, Agent or Firm:
Yutaro Kumagai



 
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