To prevent the sampling processing of an analog circuit from being affected by pulse noise generated in a digital circuit in digital/analog IC.

This circuit is divided into a digital circuit which does not contain a sampling pulse generation circuit and constitutes dominant part of a circuit scale and a digital circuit which contains the remaing parts other than the former circuit. A master clock CK is supplied to a clock CK1 and a master clock CK to a clock CK2 through a delay circuit 11. Sampling pulses SP1-SP3 generated in the sampling pulse generation part 82 are supplied to the sampling processing part 84 of the analog circuit 83. A time difference is provided between the clock K2 and the clock K1. Dominant pulse noise generated in power source lines VDD and VSS is avoided and the sampling pulse is generated at the inversion timing of the clock K1. Thus, it can be prevented that pulse noise in the digital circuit leaks into the analog circuit, a sampling error occurs and signal dignity deteriorates.